Complementary metal-oxide-semiconductor (CMOS) technology is heavily used in the manufacture of integrated circuits. A typical CMOS device includes two types of transistors, a P-type metal-oxide-semiconductor field effect transistor (MOSFET) and an N-type MOSFET. Current fabrication processes for CMOS devices use a single type of epitaxial material upon which the P-type and N-type MOSFETs are built. This means that current CMOS devices cannot optimize the materials used in each of the P-type and N-type MOSFETs.
In addition, as CMOS devices are scaled down, process complexities cause additional problems. For instance, patterning electrical contacts to the source and drain regions of each of the MOSFETs is a very difficult lithography operation due to the tight registration requirements in a small opening.
As such, a simplified process flow is needed to enable the optimization of materials used in the P-type and N-type MOSFETs and to improve the formation of electrical contacts to the CMOS device.